Drain Induced Barrier Lowering (DIBL) effect on the intrinsic capacitances of nano-scale MOSFETs

M. A. Karim; Sriramkumar Venugopalan; Yogesh Singh Chauhan; Darsen Lu; Ali Niknejad; Chenming Hu

Drain Induced Barrier Lowering (DIBL) effect on the intrinsic capacitances of nano-scale MOSFETs

M. A. Karim, Sriramkumar Venugopalan, Yogesh Singh Chauhan, Darsen Lu, Ali Niknejad, Chenming Hu

研究成果: Conference contribution

摘要

This paper presents a physical explanation of MOSFET intrinsic gate to drain capacitance (CCD) going negative due to Drain Induced Barrier Lowering (DIBL) effect. For the sub-90nm MOS devices, DIBL effect may be dominant enough to guide C_GD to negative if de-embedded from parallel extrinsic overlap, outer and inner fringing capacitances. The possibility of this phenomenon is evident from the results of our 2-D TCAD simulations of conventional bulk MOS structure. However negative capacitances lead to non-convergence issue in circuit simulators and need to be bounded in MOS devices compact models.

原文	English
主出版物標題	Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011
頁面	814-817
頁數	4
出版狀態	Published - 2011 11月 23
事件	Nanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011 - Boston, MA, United States 持續時間: 2011 6月 13 → 2011 6月 16

出版系列

名字	Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011
卷	2

Other

Other	Nanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011
國家/地區	United States
城市	Boston, MA
期間	11-06-13 → 11-06-16

All Science Journal Classification (ASJC) codes

硬體和架構
電氣與電子工程

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Karim, M. A., Venugopalan, S., Chauhan, Y. S., Lu, D., Niknejad, A., & Hu, C. (2011). Drain Induced Barrier Lowering (DIBL) effect on the intrinsic capacitances of nano-scale MOSFETs. 於 Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011 (頁 814-817). (Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011; 卷 2).

Karim, M. A. ; Venugopalan, Sriramkumar ; Chauhan, Yogesh Singh 等. / Drain Induced Barrier Lowering (DIBL) effect on the intrinsic capacitances of nano-scale MOSFETs. Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011. 2011. 頁 814-817 (Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011).

@inproceedings{539597433d2840058ad0eaa72a4abbf2,

title = "Drain Induced Barrier Lowering (DIBL) effect on the intrinsic capacitances of nano-scale MOSFETs",

abstract = "This paper presents a physical explanation of MOSFET intrinsic gate to drain capacitance (CCD) going negative due to Drain Induced Barrier Lowering (DIBL) effect. For the sub-90nm MOS devices, DIBL effect may be dominant enough to guide CGD to negative if de-embedded from parallel extrinsic overlap, outer and inner fringing capacitances. The possibility of this phenomenon is evident from the results of our 2-D TCAD simulations of conventional bulk MOS structure. However negative capacitances lead to non-convergence issue in circuit simulators and need to be bounded in MOS devices compact models.",

author = "Karim, {M. A.} and Sriramkumar Venugopalan and Chauhan, {Yogesh Singh} and Darsen Lu and Ali Niknejad and Chenming Hu",

year = "2011",

month = nov,

day = "23",

language = "English",

isbn = "9781439871393",

series = "Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011",

pages = "814--817",

booktitle = "Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011",

note = "Nanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011 ; Conference date: 13-06-2011 Through 16-06-2011",

}

Karim, MA, Venugopalan, S, Chauhan, YS, Lu, D, Niknejad, A & Hu, C 2011, Drain Induced Barrier Lowering (DIBL) effect on the intrinsic capacitances of nano-scale MOSFETs. 於 Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011. Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011, 卷 2, 頁 814-817, Nanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011, Boston, MA, United States, 11-06-13.

Drain Induced Barrier Lowering (DIBL) effect on the intrinsic capacitances of nano-scale MOSFETs. / Karim, M. A.; Venugopalan, Sriramkumar; Chauhan, Yogesh Singh 等.

Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011. 2011. p. 814-817 (Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011; 卷 2).

研究成果: Conference contribution

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T1 - Drain Induced Barrier Lowering (DIBL) effect on the intrinsic capacitances of nano-scale MOSFETs

AU - Karim, M. A.

AU - Venugopalan, Sriramkumar

AU - Chauhan, Yogesh Singh

AU - Lu, Darsen

AU - Niknejad, Ali

AU - Hu, Chenming

PY - 2011/11/23

Y1 - 2011/11/23

N2 - This paper presents a physical explanation of MOSFET intrinsic gate to drain capacitance (CCD) going negative due to Drain Induced Barrier Lowering (DIBL) effect. For the sub-90nm MOS devices, DIBL effect may be dominant enough to guide CGD to negative if de-embedded from parallel extrinsic overlap, outer and inner fringing capacitances. The possibility of this phenomenon is evident from the results of our 2-D TCAD simulations of conventional bulk MOS structure. However negative capacitances lead to non-convergence issue in circuit simulators and need to be bounded in MOS devices compact models.

AB - This paper presents a physical explanation of MOSFET intrinsic gate to drain capacitance (CCD) going negative due to Drain Induced Barrier Lowering (DIBL) effect. For the sub-90nm MOS devices, DIBL effect may be dominant enough to guide CGD to negative if de-embedded from parallel extrinsic overlap, outer and inner fringing capacitances. The possibility of this phenomenon is evident from the results of our 2-D TCAD simulations of conventional bulk MOS structure. However negative capacitances lead to non-convergence issue in circuit simulators and need to be bounded in MOS devices compact models.

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M3 - Conference contribution

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SN - 9781439871393

T3 - Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011

SP - 814

EP - 817

BT - Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011

T2 - Nanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011

Y2 - 13 June 2011 through 16 June 2011

ER -

Karim MA, Venugopalan S, Chauhan YS, Lu D, Niknejad A, Hu C. Drain Induced Barrier Lowering (DIBL) effect on the intrinsic capacitances of nano-scale MOSFETs. 於 Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011. 2011. p. 814-817. (Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011).

Drain Induced Barrier Lowering (DIBL) effect on the intrinsic capacitances of nano-scale MOSFETs

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