Dual-core virtual platform with QEMU and SystemC

Cheng Shiuan Peng, Li Chuan Chang, Chih Hung Kuo, Bin Da Liu

研究成果: Conference contribution

14 引文 斯高帕斯(Scopus)

摘要

Dual-core platforms are growing as a new industry trend as platforms with only one core cannot easily perform the diverse functions in current embedded system applications, such as smart phones. We establish an easy-to-use co-simulation dual-core virtual platform to validate the functionality of hardware and software jointly. In our platform, the hardware components are implemented by SystemC, and two ARM CPUs which are emulated by QEMU, executing the software functions. To control the data flow, BSD sockets are employed to deliver data to each component, including shared memory, hardware modules and QEMU. A thread controller is also built to handle the system thread between the different cores. We verify the dual-core virtual platform using an advanced H.264/A VC encoder SystemC model and a H.264/AVC decoder. The model is controlled by a QEMU emulated ARM CPU, and another ARM CPU executes the decoder flow.

原文English
主出版物標題2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
頁面69-72
頁數4
DOIs
出版狀態Published - 2010 12月 1
事件2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Kaohsiung, Taiwan
持續時間: 2010 11月 182010 11月 19

出版系列

名字2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program

Other

Other2010 International Symposium on Next-Generation Electronics, ISNE 2010
國家/地區Taiwan
城市Kaohsiung
期間10-11-1810-11-19

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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