In-memory key-value caches are widely used by web applications to reduce latencies of database queries. In recent years, multilevel cell (MLC) technology has been used in various emerging nonvolatile memories (NVM), allowing the building of large-scale main memory in a computing system. Building key-value caches on NVM, instead of DRAM, not only prevents cache data loss due to power outage but also improves the cache hit rate. However, it could lead to degraded performance due to the inferior write performance of NVM, compared to that of DRAM. To address this problem, previous studies focus on reducing the amount of NVM writes. In this paper, we propose Dual-KV, a method to improve performance of MLC NVM key-value caches. Different from previous studies, Dual-KV achieves the performance improvement by exploiting the write-latency/retention-time trade-off of MLC NVM. In MLC NVM, write latency increases with the retention time. The basic idea of Dual-KV is to adopt short-latency-and-short-retention writes (i.e., fast writes) for frequently updated data items while using longlatency- and-long-retention writes (i.e., slow writes) for the other data items. The experiment results show that Dual-KV improves throughput by up to 43% and 83% for single-thread and 16-thread YCSB workloads, respectively. Moreover, Dual-KV is designed to be integrated into existing key-value caches easily. Integrating Dual- KV into Memcached, a widely-used key-value cache, requires less than 30 lines of code modifications.