Economic aspects of memory built-in self-repair

Rei Fu Huang, Chao Hsun Chen, Cheng Wen Wu

研究成果: Article同行評審

26 引文 斯高帕斯(Scopus)

摘要

The demand for built-in self-repair (BISR) methodologies that improve the yield of embedded memories is growing. A typical BISR scheme requires circuit modules that perform built-in self-test (BIST), built-in redundancy analysis (BIRA), real-time address remapping, and so on. The objective of BISR design is to maximize the final yield while keeping a reasonably low hardware overhead. In this work, the authors propose cost and benefit models, and evaluate the economic effectiveness of typical memory BISR implementations. They also present a simulator for that purpose based on the proposed cost models. The results are useful for evaluating the BISR schemes and implementations. Experimental results show that memory size impacts the cost-effectiveness of BISR more than production volume does.

原文English
頁(從 - 到)164-172
頁數9
期刊IEEE Design and Test of Computers
24
發行號2
DOIs
出版狀態Published - 2007 三月 1

All Science Journal Classification (ASJC) codes

  • 硬體和架構

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