Effect of gate voltage on hot-carrier-induced on-resistance degradation in high-voltage n-type lateral diffused metal-oxide-semiconductor transistors

Shiang Yu Chen, Jone F. Chen, Kuo Ming Wu, J. R. Lee, C. M. Liu, S. L. Hsu

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

The phenomenon and mechanism of hot-carrier-induced on-resistance (R on) degradation for the n-type lateral diffused metal-oxide- semiconductor (MOS) transistors stressed under various gate voltages (V g) are investigated. Ron degradation of the device is found to be attributed to the interface state (Nit) generation in the N- drift region. Moreover, Aon degradation is almost identical for the devices stressed under medium Vg and high V g, despite the fact that bulk current of the device is much greater at high Vg bias. Such an anomalous Ron degradation is suggested to be the result of two combined factors: the magnitude of impact ionization rate and Nit generation efficiency.

原文English
頁(從 - 到)2645-2649
頁數5
期刊Japanese journal of applied physics
47
發行號4 PART 2
DOIs
出版狀態Published - 2008 4月 25

All Science Journal Classification (ASJC) codes

  • 一般工程
  • 一般物理與天文學

指紋

深入研究「Effect of gate voltage on hot-carrier-induced on-resistance degradation in high-voltage n-type lateral diffused metal-oxide-semiconductor transistors」主題。共同形成了獨特的指紋。

引用此