Effects of fin width on high-κ/metal gate bulk FinFET devices

Chien Hung Chen; Ying Chien Fang; Sheng Yuan Chu

doi:10.1049/el.2014.1117

Effects of fin width on high-κ/metal gate bulk FinFET devices

Chien Hung Chen, Ying Chien Fang, Sheng Yuan Chu

電機工程學系

研究成果: Article › 同行評審

4 引文斯高帕斯（Scopus）

摘要

The effects of silicon fin width on the electrostatic characteristics of high-κ/metal gate bulk fin field-effect transistor (FinFET) devices are investigated. Six devices with different layout fin widths and lengths are designed and fabricated. A technology computer-aided design (TCAD) simulation model with the proposed devices simplified as an equivalent circuit with three components (C_ox, C_s and R_s) indicates that for a given layout area, a narrower fin width leads to a worse flat band voltage shift and larger variation of gate capacitance due to increased substrate resistance.

原文	English
頁（從 - 到）	1160-1162
頁數	3
期刊	Electronics Letters
卷	50
發行號	16
DOIs	https://doi.org/10.1049/el.2014.1117
出版狀態	Published - 2014 7月 31

All Science Journal Classification (ASJC) codes

電氣與電子工程

存取文件

10.1049/el.2014.1117

其它文件與鏈接

引用此

@article{2ad45aa142094d1d8b8fcc52b9b38aac,

title = "Effects of fin width on high-κ/metal gate bulk FinFET devices",

abstract = "The effects of silicon fin width on the electrostatic characteristics of high-κ/metal gate bulk fin field-effect transistor (FinFET) devices are investigated. Six devices with different layout fin widths and lengths are designed and fabricated. A technology computer-aided design (TCAD) simulation model with the proposed devices simplified as an equivalent circuit with three components (Cox, Cs and Rs) indicates that for a given layout area, a narrower fin width leads to a worse flat band voltage shift and larger variation of gate capacitance due to increased substrate resistance.",

author = "Chen, {Chien Hung} and Fang, {Ying Chien} and Chu, {Sheng Yuan}",

year = "2014",

month = jul,

day = "31",

doi = "10.1049/el.2014.1117",

language = "English",

volume = "50",

pages = "1160--1162",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "Institution of Engineering and Technology",

number = "16",

}

TY - JOUR

T1 - Effects of fin width on high-κ/metal gate bulk FinFET devices

AU - Chen, Chien Hung

AU - Fang, Ying Chien

AU - Chu, Sheng Yuan

PY - 2014/7/31

Y1 - 2014/7/31

N2 - The effects of silicon fin width on the electrostatic characteristics of high-κ/metal gate bulk fin field-effect transistor (FinFET) devices are investigated. Six devices with different layout fin widths and lengths are designed and fabricated. A technology computer-aided design (TCAD) simulation model with the proposed devices simplified as an equivalent circuit with three components (Cox, Cs and Rs) indicates that for a given layout area, a narrower fin width leads to a worse flat band voltage shift and larger variation of gate capacitance due to increased substrate resistance.

AB - The effects of silicon fin width on the electrostatic characteristics of high-κ/metal gate bulk fin field-effect transistor (FinFET) devices are investigated. Six devices with different layout fin widths and lengths are designed and fabricated. A technology computer-aided design (TCAD) simulation model with the proposed devices simplified as an equivalent circuit with three components (Cox, Cs and Rs) indicates that for a given layout area, a narrower fin width leads to a worse flat band voltage shift and larger variation of gate capacitance due to increased substrate resistance.

UR - http://www.scopus.com/inward/record.url?scp=84905256729&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84905256729&partnerID=8YFLogxK

U2 - 10.1049/el.2014.1117

DO - 10.1049/el.2014.1117

M3 - Article

AN - SCOPUS:84905256729

SN - 0013-5194

VL - 50

SP - 1160

EP - 1162

JO - Electronics Letters

JF - Electronics Letters

IS - 16

ER -

Effects of fin width on high-κ/metal gate bulk FinFET devices

摘要

All Science Journal Classification (ASJC) codes

存取文件

其它文件與鏈接

指紋

引用此