Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

Po Jung Sung; Chun Jung Su; Shih Hsuan Lo; Fu Kuo Hsueh; Darsen D. Lu; Yao Jen Lee; Tien Sheng Chao

doi:10.1109/JEDS.2020.2987005

Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

Po Jung Sung, Chun Jung Su, Shih Hsuan Lo, Fu Kuo Hsueh, Darsen D. Lu, Yao Jen Lee, Tien Sheng Chao

微電子工程研究所

研究成果: Article › 同行評審

10 引文斯高帕斯（Scopus）

摘要

In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity but also significantly improve FeFET electrostatics. The experimental results indicate that FeFET with a narrow width shows weaker ferroelectric properties, and SS of sub-60 mV/dec with I_D change less than two orders of magnitude. However, FeFET with a broad channel width reveals stronger ferroelectric properties, and SS of sub-60 mV/dec is over 2 orders of magnitude of I_d. Finally, typical voltage transfer characteristics (VTCs) of a FeFET CMOS inverter with double sweeps at various V_D from 0.6 to 2 V are demonstrated. The results show that hysteresis in a FeFET CMOS inverter could have both clockwise (CW) and counter-clockwise (CCW) loops.

原文	English
文章編號	9063644
頁（從 - 到）	474-480
頁數	7
期刊	IEEE Journal of the Electron Devices Society
卷	8
DOIs	https://doi.org/10.1109/JEDS.2020.2987005
出版狀態	Published - 2020

All Science Journal Classification (ASJC) codes

生物技術
電子、光磁材料
電氣與電子工程

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10.1109/JEDS.2020.2987005

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@article{1be82a9ad5cf418d9c812129e91000dc,

title = "Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter",

abstract = "In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity but also significantly improve FeFET electrostatics. The experimental results indicate that FeFET with a narrow width shows weaker ferroelectric properties, and SS of sub-60 mV/dec with ID change less than two orders of magnitude. However, FeFET with a broad channel width reveals stronger ferroelectric properties, and SS of sub-60 mV/dec is over 2 orders of magnitude of Id. Finally, typical voltage transfer characteristics (VTCs) of a FeFET CMOS inverter with double sweeps at various VD from 0.6 to 2 V are demonstrated. The results show that hysteresis in a FeFET CMOS inverter could have both clockwise (CW) and counter-clockwise (CCW) loops.",

author = "Sung, {Po Jung} and Su, {Chun Jung} and Lo, {Shih Hsuan} and Hsueh, {Fu Kuo} and Lu, {Darsen D.} and Lee, {Yao Jen} and Chao, {Tien Sheng}",

note = "Funding Information: This work was supported by the Taiwan Semiconductor Research Institute facilities, and in part by the Ministry of Science and Technology under Grant MOST-107-2221-E-492-016-MY3, Grant 109-2923-E-492-001-MY3, Grant 108-2622-8-002-016, Grant 109-2634-F-009-029, Grant 107-2628-E-492-001-MY3, Grant 109-2639-E-009-001, and Grant 109-2923-E-492-002-MY3. Publisher Copyright: {\textcopyright} 2013 IEEE.",

year = "2020",

doi = "10.1109/JEDS.2020.2987005",

language = "English",

volume = "8",

pages = "474--480",

journal = "IEEE Journal of the Electron Devices Society",

issn = "2168-6734",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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T1 - Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

AU - Sung, Po Jung

AU - Su, Chun Jung

AU - Lo, Shih Hsuan

AU - Hsueh, Fu Kuo

AU - Lu, Darsen D.

AU - Lee, Yao Jen

AU - Chao, Tien Sheng

N1 - Funding Information: This work was supported by the Taiwan Semiconductor Research Institute facilities, and in part by the Ministry of Science and Technology under Grant MOST-107-2221-E-492-016-MY3, Grant 109-2923-E-492-001-MY3, Grant 108-2622-8-002-016, Grant 109-2634-F-009-029, Grant 107-2628-E-492-001-MY3, Grant 109-2639-E-009-001, and Grant 109-2923-E-492-002-MY3. Publisher Copyright: © 2013 IEEE.

PY - 2020

Y1 - 2020

N2 - In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity but also significantly improve FeFET electrostatics. The experimental results indicate that FeFET with a narrow width shows weaker ferroelectric properties, and SS of sub-60 mV/dec with ID change less than two orders of magnitude. However, FeFET with a broad channel width reveals stronger ferroelectric properties, and SS of sub-60 mV/dec is over 2 orders of magnitude of Id. Finally, typical voltage transfer characteristics (VTCs) of a FeFET CMOS inverter with double sweeps at various VD from 0.6 to 2 V are demonstrated. The results show that hysteresis in a FeFET CMOS inverter could have both clockwise (CW) and counter-clockwise (CCW) loops.

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Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

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