Effects of microcell layout on the performance of GaN-based high-voltage light-emitting diodes

Shuguang Li, Kin Tak Lam, Wei Chih Huang, Shoou-Jinn Chang

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)

摘要

We report the effects of microcell layout on the performances of GaN-based highvoltage light-emitting diodes (HV-LEDs). Compared with samples with an S-type layout pattern, it was found that the samples with an I-type layout pattern exhibit smaller forward voltage, larger light output power, lower thermal temperature, and better wall-plug efficiency (WPE). It was also found that we could further improve the performances of HV-LED chips by introducing extra metal fingers to enhance current spreading. Compared with the S-type sample without metal fingers, we could reduce the efficiency droop from 38.6% to 14.8% by using an I-type sample with metal fingers. Furthermore, it was found that WPE reduced by around 40% after a 1000 h aging test for the S-type sample without metal fingers. In contrast, almost no decrease in WPE could be observed from the I-type sample with metal fingers after the same aging time.

原文English
文章編號057605
期刊Journal of Photonics for Energy
5
發行號1
DOIs
出版狀態Published - 2015 一月 1

All Science Journal Classification (ASJC) codes

  • 原子與分子物理與光學
  • 可再生能源、永續發展與環境

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