Effects of postdeposition annealing on a high-k-last/gate-last integration scheme for 20 nm nMOS and pMOS

Ying Tsung Chen; Ssu I. Fu; Chien Ting Lin; Wen Tai Chiang; Shoou Jinn Chang; Mon Sen Lin; Jyh Shyang Jenq

doi:10.1116/1.4793739

Effects of postdeposition annealing on a high-k-last/gate-last integration scheme for 20 nm nMOS and pMOS

Ying Tsung Chen, Ssu I. Fu, Chien Ting Lin, Wen Tai Chiang, Shoou Jinn Chang, Mon Sen Lin, Jyh Shyang Jenq

研究成果: Article › 同行評審

4 引文斯高帕斯（Scopus）

摘要

The authors report the use of postdeposition annealing (PDA) to improve the performance of a high-k (HK)-last/gate-last integration scheme involving the use of a chemical oxide interfacial layer (IL). They find that the chemical oxide IL can form Hf-silicate at the HK/IL interface to provide a larger effective k value and a smaller equivalent oxide thickness. They also find that they can achieve a small gate leakage current density (J_g) and minimal flat-band voltage (V_fb) degradation by PDA in O₂ atmosphere. Furthermore, they find that J_g and V_fb can be further improved by optimizing the metal gate stack.

原文	English
文章編號	020604
期刊	Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics
卷	31
發行號	2
DOIs	https://doi.org/10.1116/1.4793739
出版狀態	Published - 2013 3月

All Science Journal Classification (ASJC) codes

電子、光磁材料
儀器
製程化學與技術
表面、塗料和薄膜
電氣與電子工程
材料化學

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@article{f13c0854b4004717b4fe287e36471996,

title = "Effects of postdeposition annealing on a high-k-last/gate-last integration scheme for 20 nm nMOS and pMOS",

abstract = "The authors report the use of postdeposition annealing (PDA) to improve the performance of a high-k (HK)-last/gate-last integration scheme involving the use of a chemical oxide interfacial layer (IL). They find that the chemical oxide IL can form Hf-silicate at the HK/IL interface to provide a larger effective k value and a smaller equivalent oxide thickness. They also find that they can achieve a small gate leakage current density (Jg) and minimal flat-band voltage (Vfb) degradation by PDA in O2 atmosphere. Furthermore, they find that Jg and Vfb can be further improved by optimizing the metal gate stack.",

author = "Chen, {Ying Tsung} and Fu, {Ssu I.} and Lin, {Chien Ting} and Chiang, {Wen Tai} and Chang, {Shoou Jinn} and Lin, {Mon Sen} and Jenq, {Jyh Shyang}",

note = "Funding Information: This work was supported in part by the Advanced Optoelectronic Technology Center and in part by the Center for Micro/Nano Science and Technology, NCKU, under projects from the Ministry of Education, Taiwan.",

year = "2013",

month = mar,

doi = "10.1116/1.4793739",

language = "English",

volume = "31",

journal = "Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics",

issn = "2166-2746",

publisher = "AVS Science and Technology Society",

number = "2",

}

TY - JOUR

T1 - Effects of postdeposition annealing on a high-k-last/gate-last integration scheme for 20 nm nMOS and pMOS

AU - Chen, Ying Tsung

AU - Fu, Ssu I.

AU - Lin, Chien Ting

AU - Chiang, Wen Tai

AU - Chang, Shoou Jinn

AU - Lin, Mon Sen

AU - Jenq, Jyh Shyang

N1 - Funding Information: This work was supported in part by the Advanced Optoelectronic Technology Center and in part by the Center for Micro/Nano Science and Technology, NCKU, under projects from the Ministry of Education, Taiwan.

PY - 2013/3

Y1 - 2013/3

N2 - The authors report the use of postdeposition annealing (PDA) to improve the performance of a high-k (HK)-last/gate-last integration scheme involving the use of a chemical oxide interfacial layer (IL). They find that the chemical oxide IL can form Hf-silicate at the HK/IL interface to provide a larger effective k value and a smaller equivalent oxide thickness. They also find that they can achieve a small gate leakage current density (Jg) and minimal flat-band voltage (Vfb) degradation by PDA in O2 atmosphere. Furthermore, they find that Jg and Vfb can be further improved by optimizing the metal gate stack.

AB - The authors report the use of postdeposition annealing (PDA) to improve the performance of a high-k (HK)-last/gate-last integration scheme involving the use of a chemical oxide interfacial layer (IL). They find that the chemical oxide IL can form Hf-silicate at the HK/IL interface to provide a larger effective k value and a smaller equivalent oxide thickness. They also find that they can achieve a small gate leakage current density (Jg) and minimal flat-band voltage (Vfb) degradation by PDA in O2 atmosphere. Furthermore, they find that Jg and Vfb can be further improved by optimizing the metal gate stack.

UR - http://www.scopus.com/inward/record.url?scp=84875800683&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84875800683&partnerID=8YFLogxK

U2 - 10.1116/1.4793739

DO - 10.1116/1.4793739

M3 - Article

AN - SCOPUS:84875800683

SN - 2166-2746

VL - 31

JO - Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics

JF - Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics

IS - 2

M1 - 020604

ER -

Effects of postdeposition annealing on a high-k-last/gate-last integration scheme for 20 nm nMOS and pMOS

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