Efficient architecture for Reed-Solomon decoder

Yung Kuei Lu, Ming-Der Shieh

研究成果: Conference contribution

6 引文 斯高帕斯(Scopus)

摘要

An efficient Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (RiBM) algorithm is presented in this paper. Applying the developed control scheme and the simplified boundary cell, the resulting design can significantly reduce the hardware complexity and have a high throughput rate. Compared with the related works, the proposed design has the advantage of area-time complexity. With TSMC 0.18m process, the simulation results reveal that the developed RS(255,239) decoder can operate up to 425MHz and achieve a throughput rate of 3.4Gbps with a total gate count of 12,668.

原文English
主出版物標題2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs
出版狀態Published - 2012 七月 25
事件2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan
持續時間: 2012 四月 232012 四月 25

出版系列

名字2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Other

Other2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
國家Taiwan
城市Hsinchu
期間12-04-2312-04-25

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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