Efficient built-in redundancy analysis for embedded memories with 2-D redundancy

Shyue Kung Lu, Yu Chen Tsai, Chih Hsien Hsu, Kuo Hua Wang, Cheng Wen Wu

研究成果: Article同行評審

85 引文 斯高帕斯(Scopus)

摘要

A novel redundant mechanism is proposed for embedded memories in this paper. Redundant rows and columns are added into the memory array as in the conventional approaches. However, the redundant rows and columns are divided into row blocks and column blocks, respectively. The reconfiguration is performed at the row (column) block level instead of the conventional row (column) level. Based on the proposed redundant mechanism, we first show that the complexity of the redundancy allocation problem is NP-complete. Thereafter, an extended local repair-most (ELRM) algorithm suitable for built-in implementation is proposed. The complexity of the ELRM algorithm is O(N), where N denotes the number of memory cells. According to the simulation results, the hardware overhead for implementing this algorithm is below 0.17% for a 1024 × 2048-b SRAM. Due to the efficient usage of the redundant elements, the manufacturing yield, repair rate, and reliability can be improved significantly.

原文English
頁(從 - 到)34-42
頁數9
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
14
發行號1
DOIs
出版狀態Published - 2006 一月 1

All Science Journal Classification (ASJC) codes

  • 軟體
  • 硬體和架構
  • 電氣與電子工程

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