Efficient diagnostic fault simulation for sequential circuits

Jer Min Jou, Shung Chih Chen

研究成果: Conference article同行評審

摘要

In this paper, an efficient diagnostic fault simulator for sequential circuits is proposed. In it, a two-level optimization technique is developed and used to prompt the processing speed. In the first high level, an efficient list, which stores the indistinguishable faults so far for each fault during simulation, and the list maintaining algorithm are applied, thus reduces a great deal of diagnostic comparisons among all pairs of faults. In the second low level, a bit-parallel comparison is developed to speed up the comparing process. Therefore, the different diagnostic measure reports for a given test set can be generated very quickly. In addition, the simulator is extended to diagnose the single stuck-at device fault correctly. Experimental results show that our method achieves a significant speedup compared to previous methods.

原文English
頁(從 - 到)94-99
頁數6
期刊Proceedings of the Asian Test Symposium
出版狀態Published - 1994 12月 1
事件Proceedings of the 3rd Asian Test Symposium - Nara, Jpn
持續時間: 1994 11月 151994 11月 17

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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