Efficient global strategy for designing and testing scanned sequential circuits

B. D. Liu, P. C. Chen, J. F. Wang

研究成果: Article同行評審

摘要

Previous approaches to scan design have tried individually to enhance the abilities of test generation algorithm and scan cell selection strategy in order to reduce extra costs associated with the time spent on testing. In contrast, a global strategy which takes care of the close relationship between these factors and combines a new scan structure is proposed. Two assertions for the design of test generator are also proposed, and a fault list oriented test generation algorithm is developed in accordance with these two assertions. A simulation-based partial scan methodology is finally introduced for selecting the suitable scanning flip-flops through the utilization of dynamic information generated during fault simulation. Experimental results show that the proposed strategy speeds up test generation and reduces the amount of test application time.

原文English
頁(從 - 到)170-176
頁數7
期刊IEE Proceedings: Computers and Digital Techniques
142
發行號2
DOIs
出版狀態Published - 1995 三月 1

All Science Journal Classification (ASJC) codes

  • 理論電腦科學
  • 硬體和架構
  • 計算機理論與數學

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