Efficient management of in-place path metric update and its implementation for Viterbi decoders

Ming Der Shieh, Ming Hwa Sheu, Chien Ming Wu, Wann Shyang Ju

研究成果: Conference article同行評審

10 引文 斯高帕斯(Scopus)

摘要

The in-place path metric scheduling is known as an efficient approach for sequential processing of the trellis, where the number of add_compare_select (ACS) units or processors is less than the number of states. In this paper, a systematic approach to partitioning a centralized memory into several banks to increase the memory bandwidth for in-place path metric update in Viterbi decoders is presented. Similar concepts can be extended to distribute the memory banks into ACS units if the ACS units are scheduled correspondingly to keep the interconnection minimal. Implementation results show that in terms of trade-off between hardware overhead and required memory bandwidth, an expected performance improvement can be achieved based on the proposed technique, especially for the trellis with a long constraint length.

原文English
頁(從 - 到)449-452
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
4
出版狀態Published - 1998 一月 1
事件Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA
持續時間: 1998 五月 311998 六月 3

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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