The in-place path metric scheduling is known as an efficient approach for sequential processing of the trellis, where the number of add_compare_select (ACS) units or processors is less than the number of states. In this paper, a systematic approach to partitioning a centralized memory into several banks to increase the memory bandwidth for in-place path metric update in Viterbi decoders is presented. Similar concepts can be extended to distribute the memory banks into ACS units if the ACS units are scheduled correspondingly to keep the interconnection minimal. Implementation results show that in terms of trade-off between hardware overhead and required memory bandwidth, an expected performance improvement can be achieved based on the proposed technique, especially for the trellis with a long constraint length.
|頁（從 - 到）||449-452|
|期刊||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版狀態||Published - 1998 一月 1|
|事件||Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA|
持續時間: 1998 五月 31 → 1998 六月 3
All Science Journal Classification (ASJC) codes