Efficient path metric access for reducing interconnect overhead in viterbi decoders

Ming-Der Shieh, Tai Ping Wang, Chien Ming Wu, Chun Ming Huang

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

Efficient management of the path metric memory and minimization of interconnection networks between the memory and add_compare_select unit (ACSU) are always the key concerns on the design and implementation of Viterbi decoders. In this paper, we derive a set of simple equations to partition the memory into P banks such that the equivalent memory bandwidth can be increased with very simple interconnection networks. Compared with the previous work, our proposed approach reveals the following superiority: (1) Each memory bank can be treated as a local memory of a specific ACS; thus, the interconnection network is simplified. (2) The P memory banks can be merged into only two pseudobanks regardless of the number of ACS operations. This not only further reduces the hardware requirements of address generation, but also makes smaller the required memory space.

原文English
主出版物標題ISCAS 2006
主出版物子標題2006 IEEE International Symposium on Circuits and Systems, Proceedings
頁面4815-4818
頁數4
出版狀態Published - 2006 十二月 1
事件ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
持續時間: 2006 五月 212006 五月 24

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Other

OtherISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
國家/地區Greece
城市Kos
期間06-05-2106-05-24

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

指紋

深入研究「Efficient path metric access for reducing interconnect overhead in viterbi decoders」主題。共同形成了獨特的指紋。

引用此