This paper presents a multi-mode Reed-Solomon decoder design based on the reformulated inversionless Berlekamp-Massey algorithm. We show how to effectively improve the hardware utilization of the decoder and how to simplify the routing network in conventional multi-mode decoder design. The developed coefficient-selector-free multi-mode arrangement, make the decoder area-efficient and gives it a very simple and regular interconnect topology, making the decoder very suitable for VLSI realization. Experimental results show that for codewords of length n < 255 with t-error-correcting capabilities, 0<t≤8, the throughput rate of our decoder, implemented on a 0.18um process, can reach 3.2 Gbps at an operating frequency of 400 MHz with a total gate count of 22,931. Moreover, the hardware overhead of the developed multi-mode decoder is only 13.4% compared to our single-mode design for t = 8. Compared to the existing work based on the extended Euclidean algorithm for multi-mode applications, our design provides both area and speed advantages. Using the developed generator, we implemented a multi-mode decoder that can be applied to seven existing standards to demonstrate the regularity and flexibility of our design.
|頁（從 - 到）||503-516|
|期刊||International Journal of Electrical Engineering|
|出版狀態||Published - 2009 十二月 1|
All Science Journal Classification (ASJC) codes