Efficient scissoring scheme for scanline-based rendering of 2D vector graphics

Wen Ching Lin, Jheng Hao Ye, Der Wei Yang, Si Yu Huang, Ming-Der Shieh, Jonas Wang

研究成果: Paper同行評審

1 引文 斯高帕斯(Scopus)

摘要

This work presents a look-up table-based (LUT-based) algorithm for scanline-based rendering of OpenVG. The proposed method can deal with arbitrary number of scissoring rectangles. The rasterization and scissoring in the proposed architecture can be performed concurrently to reduce rendering time. The scanline-size buffers used as scissoring LUTs result in low area overhead. Moreover, a linked list structure of scissoring rectangles is proposed in order that only the scissoring rectangles interacted with the processing scanline are accessed to increase bus efficiency and reduce power consumption. Implementation results based on TSMC 0.13-μm CMOS technology show that the proposed rasterization design with LUT-based scissoring can operate at 200 MHz with 77K gate counts. The proposed design can render 16.8 tiger images with 392×483 resolution per second assuming ideal bus latency. Compared to existing works, the proposed design achieves a smaller area and more functionality for higher display resolution with comparable throughput.

原文English
頁面766-769
頁數4
DOIs
出版狀態Published - 2012 九月 28
事件2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
持續時間: 2012 五月 202012 五月 23

Other

Other2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
國家/地區Korea, Republic of
城市Seoul
期間12-05-2012-05-23

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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