Efficient testing and design-for-testability schemes for multimedia cores: A case study on DCT circuits

研究成果: Paper

2 引文 (Scopus)

摘要

Efficient test generation methods and design-for-testability schemes are critical to ensure the quality of multimedia cores. By investigating the potential test problems existing in these cores, this paper presents a series of efficient test methods to significantly reduce the test application time for these cores while obtaining 100% fault coverage. The test development procedure is demonstrated by employing a well-known 2-D discrete cosine transform (DCT) circuit that is implemented in the typical row-column decomposition method. The 100% fault coverage is first achieved by appropriately modifying the original design, including scan design insertion and some ad hoc revisions. We then apply the recently-developed input reduction method and the broadcasting scan method to overcome the deficiency of long test application time when inserting scan design into the circuits. With these two methods, the test application time can be reduced to 6.8% of those required by the single full scan designs, while only 7.9% area overhead is needed.

原文English
頁面177-180
頁數4
出版狀態Published - 2004 十二月 1
事件2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
持續時間: 2004 十二月 62004 十二月 9

Other

Other2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
國家Taiwan
城市Tainan
期間04-12-0604-12-09

指紋

Design for testability
Discrete cosine transforms
Networks (circuits)
Testing
Broadcasting
Decomposition

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此文

Shieh, M. D., Shen, S. C., Lin, Y. C., & Lee, K. J. (2004). Efficient testing and design-for-testability schemes for multimedia cores: A case study on DCT circuits. 177-180. 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.
Shieh, Ming Der ; Shen, Sheng Chih ; Lin, You Chung ; Lee, Kuen Jong. / Efficient testing and design-for-testability schemes for multimedia cores : A case study on DCT circuits. 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.4 p.
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Shieh, MD, Shen, SC, Lin, YC & Lee, KJ 2004, 'Efficient testing and design-for-testability schemes for multimedia cores: A case study on DCT circuits', 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan, 04-12-06 - 04-12-09 頁 177-180.

Efficient testing and design-for-testability schemes for multimedia cores : A case study on DCT circuits. / Shieh, Ming Der; Shen, Sheng Chih; Lin, You Chung; Lee, Kuen Jong.

2004. 177-180 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.

研究成果: Paper

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Shieh MD, Shen SC, Lin YC, Lee KJ. Efficient testing and design-for-testability schemes for multimedia cores: A case study on DCT circuits. 2004. 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.