Efficient thread architecture for a distributed shared memory on symmetric multiprocessor clusters

Jyh Biau Chang, Y. J. Tsai, C. K. Shieh, P. C. Chung

研究成果: Paper同行評審

3 引文 斯高帕斯(Scopus)

摘要

The purpose of this paper is to demonstrate an efficient thread architecture for a distributed shared memory (DSM) system on symmetric multiprocessor (SMP) clusters. For DSM systems on SMP, how to utilize the processors efficiently without wasting available computational power is a major issue. In this paper, we discuss three approaches that use the process, the kernel-level thread, and the user-level thread to map application threads onto execution entities respectively. Considering the advantages and disadvantages of each method, we construct our thread package by combining both the user-level thread and the kernel-level thread. User-level threads correspond to application threads and kernel-level threads schedule these user-level threads across multiple processors. Threads are light-weighted and can be migrated in our thread package. With this thread architecture, our DSM system performs well in elementary experiments.

原文English
頁面816-823
頁數8
出版狀態Published - 1998
事件Proceedings of the 1998 International Conference on Parallel and Distributed Systems, ICPADS - Tainan, China
持續時間: 1998 12月 141998 12月 16

Other

OtherProceedings of the 1998 International Conference on Parallel and Distributed Systems, ICPADS
城市Tainan, China
期間98-12-1498-12-16

All Science Journal Classification (ASJC) codes

  • 硬體和架構

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