TY - JOUR
T1 - Efficient VLSI Architecture for Edge-Oriented Demosaicking
AU - Lien, Chih Yuan
AU - Yang, Fu Jhong
AU - Chen, Pei Yin
AU - Fang, Yi Wen
N1 - Publisher Copyright:
© 1991-2012 IEEE.
PY - 2018/8
Y1 - 2018/8
N2 - Color filter array interpolation, also known as demosaicking and 'debayering,' is a crucial process for image reconstruction in digital still cameras. This paper presents an edge-oriented demosaicking method and an efficient very-large-scale integration (VLSI) architecture for color interpolation. The design uses simple operations (addition, subtraction, shift, and comparator) and nearest neighboring pixels to catch the color difference and edges. The required line buffering of the proposed design is four lines; therefore, its hardware cost is low. Our extensive experiments revealed that the proposed technique preserved edge features and exhibited excellent quantitative evaluation and visual quality performances. Compared with the previous VLSI implementations, the proposed design achieved superior image qualities. The synthesis results revealed that by using Taiwan Semiconductor Manufacturing Company 0.18- μ m technology, the proposed design yields a processing rate of approximately 200M samples per second.
AB - Color filter array interpolation, also known as demosaicking and 'debayering,' is a crucial process for image reconstruction in digital still cameras. This paper presents an edge-oriented demosaicking method and an efficient very-large-scale integration (VLSI) architecture for color interpolation. The design uses simple operations (addition, subtraction, shift, and comparator) and nearest neighboring pixels to catch the color difference and edges. The required line buffering of the proposed design is four lines; therefore, its hardware cost is low. Our extensive experiments revealed that the proposed technique preserved edge features and exhibited excellent quantitative evaluation and visual quality performances. Compared with the previous VLSI implementations, the proposed design achieved superior image qualities. The synthesis results revealed that by using Taiwan Semiconductor Manufacturing Company 0.18- μ m technology, the proposed design yields a processing rate of approximately 200M samples per second.
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U2 - 10.1109/TCSVT.2017.2693027
DO - 10.1109/TCSVT.2017.2693027
M3 - Article
AN - SCOPUS:85051231004
SN - 1051-8215
VL - 28
SP - 2038
EP - 2047
JO - IEEE Transactions on Circuits and Systems for Video Technology
JF - IEEE Transactions on Circuits and Systems for Video Technology
IS - 8
M1 - 7896513
ER -