TY - GEN
T1 - Efficient VLSI design for SIFT feature description
AU - Lin, Yi Ming
AU - Yeh, Chun Hsien
AU - Yen, Sheng Hung
AU - Ma, Ching Hsuan
AU - Chen, Pei Yin
AU - Jay Kuo, C. C.
PY - 2010
Y1 - 2010
N2 - The scale invariant feature transform (SIFT) is a very efficient algorithm to extract and describe distinctive invariant features from images, and usually applied for many image applications such as object recognition, robotic mapping, and navigation. In the SIFT computation, the complexity of the feature description is quite high. Hence, it is desirable to have an efficient VLSI architecture to compute the feature descriptor quickly. We first investigate the performance analysis for SIFT and then employ the proper hardware circuit to implement the feature description process. Besides, the pipe lining technique is adopted to increase the speed of our design. Synthesis results show that the proposed circuit contains 555,062 transistors by using the TSMC 0.13/lm cell library. It works with a clock rate of 200 MHz and can support the throughput rate of about 65300 SIFT descriptors per second in real time.
AB - The scale invariant feature transform (SIFT) is a very efficient algorithm to extract and describe distinctive invariant features from images, and usually applied for many image applications such as object recognition, robotic mapping, and navigation. In the SIFT computation, the complexity of the feature description is quite high. Hence, it is desirable to have an efficient VLSI architecture to compute the feature descriptor quickly. We first investigate the performance analysis for SIFT and then employ the proper hardware circuit to implement the feature description process. Besides, the pipe lining technique is adopted to increase the speed of our design. Synthesis results show that the proposed circuit contains 555,062 transistors by using the TSMC 0.13/lm cell library. It works with a clock rate of 200 MHz and can support the throughput rate of about 65300 SIFT descriptors per second in real time.
UR - http://www.scopus.com/inward/record.url?scp=78751564110&partnerID=8YFLogxK
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U2 - 10.1109/ISNE.2010.5669202
DO - 10.1109/ISNE.2010.5669202
M3 - Conference contribution
AN - SCOPUS:78751564110
SN - 9781424466948
T3 - 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
SP - 48
EP - 51
BT - 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
T2 - 2010 International Symposium on Next-Generation Electronics, ISNE 2010
Y2 - 18 November 2010 through 19 November 2010
ER -