Efficient VLSI design for SIFT feature description

Yi Ming Lin, Chun Hsien Yeh, Sheng Hung Yen, Ching Hsuan Ma, Pei Yin Chen, C. C. Jay Kuo

研究成果: Conference contribution

9 引文 斯高帕斯(Scopus)

摘要

The scale invariant feature transform (SIFT) is a very efficient algorithm to extract and describe distinctive invariant features from images, and usually applied for many image applications such as object recognition, robotic mapping, and navigation. In the SIFT computation, the complexity of the feature description is quite high. Hence, it is desirable to have an efficient VLSI architecture to compute the feature descriptor quickly. We first investigate the performance analysis for SIFT and then employ the proper hardware circuit to implement the feature description process. Besides, the pipe lining technique is adopted to increase the speed of our design. Synthesis results show that the proposed circuit contains 555,062 transistors by using the TSMC 0.13/lm cell library. It works with a clock rate of 200 MHz and can support the throughput rate of about 65300 SIFT descriptors per second in real time.

原文English
主出版物標題2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
頁面48-51
頁數4
DOIs
出版狀態Published - 2010
事件2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Kaohsiung, Taiwan
持續時間: 2010 11月 182010 11月 19

出版系列

名字2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program

Other

Other2010 International Symposium on Next-Generation Electronics, ISNE 2010
國家/地區Taiwan
城市Kaohsiung
期間10-11-1810-11-19

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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