With high-speed computers and wireless communications system become more popular in the electronic market, these communication-oriented products require high packaging densities, clock rates and higher switching speeds over Gb/s. A multilayer flip-chip Ball grid array (FCBGA) package used for applications running at more than 1 Gb/s has been characterized in this work. Electrical characterization of the package becomes essential beyond 1 GHz considering that the interconnections on the package behave not only just as interconnections but also as transmission lines. In this paper, we present the measurement and simulation results for interconnection of an FCBGA package using the time domain reflectometry (TDR) method. Simulation and measurement results are compared to establish a proper equivalent circuit model of the FCBGA interconnections. The parasitics of the power network can be measured through TDR, vector network analyzer (VNA) and impedance analyzer (IA). The complete models generated in this work are targeted for high-speed system-on-chip (SOC) devices that have a wide range of uses across commercial electronic applications.
|頁（從 - 到）||216-225|
|期刊||Journal of Microelectronics and Electronic Packaging|
|出版狀態||Published - 2006|
All Science Journal Classification (ASJC) codes