Energy-aware partitioning for on-chip bus architecture using a multi-objective genetic algorithm

Lih Yih Chiou, Yi Siou Chen, Ya Lun Jian

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

Incorporating power management during partitioning at the system level contributes considerably to energy efficient architecture. Designers commonly implement systems as a mix of partitioning blocks of various sizes, connected using bus interconnection architecture. Therefore, the use of a partitioning approach that partitions a system with the greatest possible idle time on a dedicated interconnection architecture has become unpractical for power management development. This work presents a novel energy-aware hardware clustering algorithm with a performance estimator for on-chip bus based architectures during high level synthesis, to enhance the quality of solutions for implementing power management systems. Experimental results obtained in four cases reveal that the proposed strategy generates a wide range of cost-effective solutions and is highly effective for today's hardware systems.

原文English
主出版物標題Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
頁面345-348
頁數4
DOIs
出版狀態Published - 2011 6月 28
事件2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan
持續時間: 2011 4月 252011 4月 28

出版系列

名字Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Other

Other2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
國家/地區Taiwan
城市Hsinchu
期間11-04-2511-04-28

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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