Energy-efficient dual-edge-triggered level converting flip flops with symmetry in setup times and insensitivity to output parasitics

Lih Yih Chiou, Shien Chun Luo

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)

摘要

Level converting flip-flops (LCFFs) are crucial components for multisupply systems as interfaces between different voltage islands. The proposed energy-efficient LCFFs reduce the power consumption of clock networks with dual-edge triggering, support sleep mode of power management mechanisms with data retention, and have symmetry in setup times and insensitivity to output parasitics. With all these features, the proposed LCFFs have 19% and 38% lower power-delay product than the conventional LCFF, as demonstrated by postlayout simulation results.

原文English
文章編號4814496
頁(從 - 到)1659-1663
頁數5
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
17
發行號11
DOIs
出版狀態Published - 2009 十一月

All Science Journal Classification (ASJC) codes

  • 軟體
  • 硬體和架構
  • 電氣與電子工程

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