Energy-efficient hardware architecture and VLSI implementation of a polyphase channelizer with applications to subband adaptive filtering

Yongtao Wang, Hamid Mahmoodi, Lih Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy

研究成果: Article同行評審

9 引文 斯高帕斯(Scopus)

摘要

Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementation of polyphase channelizer, integrating algorithmic, architectural and circuit level design techniques. At algorithm level, low complexity polyphase channelizer architecture is derived using multirate signal processing approach. To reduce the computational complexity in polyphase filters, computation sharing differential coefficient (CSDC) method is effectively used as an architectural level technique. The main idea of CSDC is to combine the strength of augmented differential coefficient method and subexpression sharing. Efficient circuit-level techniques: low power commutator implementation, dual-VDD scheme and novel level-converting flip-flop (LCFF), are also used to further reduce the power dissipation. The proposed polyphase channelizer consumes 352 mW power with throughput of 480 million samples per second (MSPS). A test chip has been fabricated in 0.18 μm CMOS technology and its functionality is verified. Chip measurement results show that the dual-VDD implementation achieves a total power saving of 2.7 X.

原文English
頁(從 - 到)125-137
頁數13
期刊Journal of Signal Processing Systems
58
發行號2
DOIs
出版狀態Published - 2010 2月

All Science Journal Classification (ASJC) codes

  • 控制與系統工程
  • 理論電腦科學
  • 訊號處理
  • 資訊系統
  • 建模與模擬
  • 硬體和架構

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