Enhancement of CMOSFETs performance by utilizing SACVD-based shallow trench isolation for the 40-nm node and beyond

Yao Tsung Huang, San Lein Wu, Shoou Jinn Chang, Chin Kai Hung, Tzu Juei Wang, Cheng Wen Kuo, Cheng Tung Huang, Osbert Cheng

研究成果: Article同行評審

4 引文 斯高帕斯(Scopus)

摘要

This paper reports an improved densification anneal process for sub-atmospheric chemical vapor deposition (SACVD)-based shallow trench isolation (STI) to enhance CMOSFETs performance for 40-nm node and beyond. The improved STI densification process is demonstrated to generate a lower compressive stress in the active area as compared to the Standard STI process used in 40 nm technology. For nMOS devices with the improved densification process, the reduction of STI compressive stress is beneficial to the electron mobility and leads to an enhancement of on-current ($I-{{\rm ON}}$ ). In addition, the $I-{{\rm ON}}$ enhancements would significantly increase with shrinking the device dimensions (gate width and source/drain length). On the other hand, the improved densification process would not degrade the pMOSFETs performance resulting from the very small piezoresistance coefficients for 100 channel direction. The superior junction leakage characteristics for the junction diodes with the improved anneal process can further verify the lower STI-induced compressive stress due to the less energy bandgap narrowing. Hence, the improved STI process can be adopted in 40-nm CMOS technology and beyond, where device structures have very small active areas.

原文English
文章編號5439751
頁(從 - 到)433-438
頁數6
期刊IEEE Transactions on Nanotechnology
10
發行號3
DOIs
出版狀態Published - 2011 五月

All Science Journal Classification (ASJC) codes

  • 電腦科學應用
  • 電氣與電子工程

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