Evaluation of sequential-in-random-out memory device

C. Y. Chang, C. K. Shieh, T. W. Hou

研究成果: Article同行評審

摘要

The buffering of data is a potential bottleneck to performance. In general, the buffer can be implemented either by FIFO or dual-port RAM, which are both two-port memory devices. In the Letter a classification of buffers is proposed. According to the classification, a new two-port memory device with the sequential-in-random-out feature is introduced. Simulation results show that 45% time, at most, could be saved, as compared to a FIFO buffer.

原文English
頁(從 - 到)620-621
頁數2
期刊Electronics Letters
31
發行號8
DOIs
出版狀態Published - 1995 4月 13

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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