Fabrication and analysis of a Si/Si0.55Ge0.45 heterojunction line tunnel FET

Amey M. Walke, Anne Vandooren, Rita Rooyackers, Daniele Leonelli, Andriy Hikavyy, Roger Loo, Anne S. Verhulst, Kuo Hsing Kao, Cedric Huyghebaert, Guido Groeseneken, Valipe Ramgopal Rao, Krishna K. Bhuwalka, Marc M. Heyns, Nadine Collaert, Aaron Voon Yew Thean

研究成果: Article同行評審

85 引文 斯高帕斯(Scopus)

摘要

This paper presents a new integration scheme to fabricate a Si/Si 0.55 Ge0.45 heterojunction line tunnel field effect transistor (TFET). The device shows an increase in tunneling current with gate length. The 1-μm gate length device shows on current in excess of 20 μA/μm at VGS=VDS=1.2~V. Low-temperature measurements, performed to suppress trap-assisted tunneling (TAT), reveal the point subthreshold swing as low as 22 mV/dec at 78 K. Field-induced quantum confinement effects are found to increase the tunneling onset voltage by ∼0.35~V. Variation of the tunneling onset voltage measured experimentally is correlated to variation in the pocket thickness and its doping concentration. Small geometry devices were found to be more susceptible to microvariations in the pocket thickness and doping concentration.

原文English
文章編號6727530
頁(從 - 到)707-715
頁數9
期刊IEEE Transactions on Electron Devices
61
發行號3
DOIs
出版狀態Published - 2014 3月

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 電氣與電子工程

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