TY - GEN
T1 - Failure Mechanism Analysis of SiC MOSFETs in Unclamped Inductive Switching Conditions
AU - Ren, Na
AU - Wang, Kang L.
AU - Wu, Jiupeng
AU - Xu, Hongyi
AU - Sheng, Kuang
N1 - Publisher Copyright:
© 2019 IEEE.
Copyright:
Copyright 2019 Elsevier B.V., All rights reserved.
PY - 2019/5
Y1 - 2019/5
N2 - In this work, avalanche ruggedness and failure mechanism of SiC MOSFET in single-pulse Unclamped Inductive Switching (UIS) tests are investigated and compared with that of Si IGBT. The experimental results show that the avalanche energy of SiC MOSFET is only 30% that of Si IGBT due to the much smaller chip size (1/7 that of Si IGBT). To improve the avalanche capability of SiC MOSFET, the failure mechanism is analyzed. First, junction temperature in the UIS test is calculated through modeling. The maximum junction temperatures reach 650 K and 490 K in SiC MOSFET and Si IGBT, respectively. Then, BJT latch-up probability is analyzed with an analytical model. It is demonstrated that BJT latch-up can be triggered at the failure temperature (650 K) in SiC MOSFET, whereas it can be eliminated in Si IGBT due to the much deeper P+ body structure. Based on the analyses, the device structure optimization is proposed for SiC MOSFET to prevent the BJT latch-up and enable avalanche capability improvement.
AB - In this work, avalanche ruggedness and failure mechanism of SiC MOSFET in single-pulse Unclamped Inductive Switching (UIS) tests are investigated and compared with that of Si IGBT. The experimental results show that the avalanche energy of SiC MOSFET is only 30% that of Si IGBT due to the much smaller chip size (1/7 that of Si IGBT). To improve the avalanche capability of SiC MOSFET, the failure mechanism is analyzed. First, junction temperature in the UIS test is calculated through modeling. The maximum junction temperatures reach 650 K and 490 K in SiC MOSFET and Si IGBT, respectively. Then, BJT latch-up probability is analyzed with an analytical model. It is demonstrated that BJT latch-up can be triggered at the failure temperature (650 K) in SiC MOSFET, whereas it can be eliminated in Si IGBT due to the much deeper P+ body structure. Based on the analyses, the device structure optimization is proposed for SiC MOSFET to prevent the BJT latch-up and enable avalanche capability improvement.
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U2 - 10.1109/ISPSD.2019.8757657
DO - 10.1109/ISPSD.2019.8757657
M3 - Conference contribution
AN - SCOPUS:85073910227
T3 - Proceedings of the International Symposium on Power Semiconductor Devices and ICs
SP - 183
EP - 186
BT - 2019 31st International Symposium on Power Semiconductor Devices and ICs, ISPSD 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 31st International Symposium on Power Semiconductor Devices and ICs, ISPSD 2019
Y2 - 19 May 2019 through 23 May 2019
ER -