Fault Models and Test Algorithms for Multi-Level Cell (MLC) Crossbar RRAM

Cheng-Wen Wu, K.-W. Hou

研究成果: Conference contribution

原文English
主出版物標題VLSI Test Technology Workshop (VTTW)
出版地Nantou
出版狀態Published - 2017 七月

引用此

Wu, C-W., & Hou, K-W. (2017). Fault Models and Test Algorithms for Multi-Level Cell (MLC) Crossbar RRAM. 於 VLSI Test Technology Workshop (VTTW)