Fault Pattern Oriented Defect Diagnosis for Memories

Chih Wea Wang, Kuo Liang Cheng, Jih Nung Lee, Yung Fa Chou, Chih Tsun Huang, Cheng Wen Wu, Frank Huang, Hong-Tzer Yang

研究成果: Conference article同行評審

22 引文 斯高帕斯(Scopus)


Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-chip (SOC) product development and yield ramp-up. Conventional FA based on bitmaps and the experiences of the FA engineer is time consuming and error prone. The increasing time-to-volume pressure on semiconductor products calls for new development flow that enables the product to reach a profitable yield level as soon as possible. Demand in methodologies that allow FA automation thus increases rapidly in recent years. This paper proposes a systematic diagnosis approach based on failure patterns and functional fault models of semiconductor memories. By circuit-level simulation and analysis, we have also developed a fault pattern generator. Defect diagnosis and FA can be performed automatically by using the fault patterns, reducing the time in yield improvement. The main contribution of the paper is thus a methodology and procedure for accelerating FA and yield optimization for semiconductor memories.

頁(從 - 到)29-38
期刊IEEE International Test Conference (TC)
出版狀態Published - 2003
事件Proceedings International Test Conference 2003 - Charlotte, NC, United States
持續時間: 2003 9月 302003 10月 2

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程
  • 應用數學


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