Finite element analysis of multi-level interconnection under cyclic thermomechanical loads

Kuo Tsai Wu, Sheng Jye Hwang, Huei Huang Lee, Bing Yeh Lin

研究成果: Article同行評審

摘要

In manufacturing processing, using copper wire for connecting each micro-device and constructing logical circuit to reduce RC time delay is a major technique. However, during fabrication, the thermo-mechanical mismatch between materials generate high stress, which lead to stress-induced voids, cracks, and interface delamination, all of which we strongly affect the reliability of integrated circuits. This study utilizes materials mechanics, fracture mechanics, and the finite element method to analyze cracking and interfacial delamination of thin films and interconnect structures and to determine the strain energy release rate within such structures under cyclic thermal loading. In addition, parametric studies that analyze the influence of each physical parameter (e.g., temperature, geometry, and properties of low-k materials) on the stress, strain energy release rate, and crack growth. Based on these investigations, we optimize size parameters of the interconnect structure. The results show that mismatch of thermo-mechanical behavior between different materials and spaces on wires are significant factors for generating high stresses. It is also found that selecting the low-k materials with higher Young’s modulus and lower coefficient of thermal expansion can avoid caused high stress. The temperature range is on focus improve the reliability of interconnect structures, and variations energy release rate could prevent interfacial delamination of thin films.

原文English
頁(從 - 到)1003-1016
頁數14
期刊Microsystem Technologies
24
發行號2
DOIs
出版狀態Published - 2018 二月 1

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 凝聚態物理學
  • 硬體和架構
  • 電氣與電子工程

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