High-k dielectrics are crucial in scaled CMOS technology because their large physical thickness can suppress gate tunneling leakage current at a scaled equivalent oxide thickness (EOT). For the past decade, hafnium-based gate dielectrics (HfO2 or Hf-based oxides) have been introduced to mass-production by commercial chip-makers. In the meantime, metal gates were also explored to improve the poly-Si depletion effect polysilicon gate electrodes in high performance logic devices at 45 nm node technology and beyond. However, the development of metal gates with Fermi level near the Si band edges has been difficult on Hf-based gate dielectrics, which can be attributed to several possible factors including Fermi level pinning and interfacial dipole formation.[1,2] Recently, the use of thin cap layers that are inserted between the gate metal and dielectric has been shown to cause negative flatband voltage (Vfb) shift and stabilize low VTH simultaneously. A major challenge with cap layers is to achieve adequate effective work function shifts without large increases in EOT (ΔEOT). Atomic layer deposition (ALD) La2O3 cap layer is a promising candidate for n-channel devices due to its relatively high dielectric constant of ∼17  and strong bond polarization. Essentially, ALD is one precursor dominated process , successful applications of ALD in advanced CMOS technology should depend on whether appropriate precursor can be utilized. In this work, effects of the La2O3 cap layer interposed in Si/SiO2/HfO2/TiN high-k gate dielectric stacks prepared from two different ALD lanthanum precursors, La(fAMD)3 and La(thd)3, in tuning V fb and ΔEOT are investigated. The values of Δ Vfband ΔEOT as high as 0.45 V and 0.055 nm were achieved by a 1-nm-thick La2O3 cap layer.