Forecasting Silicon Superconducting Properties with CMOS-Compatible Processes at Room Temperature

The development of silicon-based superconducting devices has traditionally required time-consuming iterative cycles, involving material optimization, process refinement, and electrical testing at cryogenic temperatures. To accelerate this process, a reliable in-line method capable of predicting superconducting properties without entering the cryogenic regime and using room-temperature measurements is highly desirable. In this study, we investigate the material and electrical characteristics of superconducting silicon fabricated under four different annealing conditions, each defined by a specific capping layer thickness. Free-carrier density is extracted at room temperature via differential Hall effect metrology, while room-temperature sheet resistances and superconducting critical temperatures are measured using a four-point probe and cryogenic electrical characterization in a dilution refrigerator, respectively. A clear correlation is established among these physical quantities across all conditions used in our investigation, with the free-carrier density extracted at room temperature emerging as the key linking parameter. This correlation provides a physically grounded and experimentally accessible strategy for expediting the optimization of CMOS-compatible superconducting silicon devices.