Formation of Hump Effect Due to Top-Gate Bias Stress in Organic Thin-Film Transistors

Hong Chih Chen, Yu Ching Tsao, An Kuo Chu, Hui Chun Huang, Wei Chih Lai, Guan Fu Chen, Shin Ping Huang, Ting Chang Chang, Po Hsun Chen, Jian Jie Chen, Chuan Wei Kuo, Kuan Ju Zhou, Yang Hao Hung

研究成果: Article

摘要

This study investigated the reliability of top-gate p-type organic thin-film transistors in vacuum under positive bias stress-induced and positive bias illumination stress-induced instability degradation. The manufacturing process suggested that sidewall dielectric insulating layers are thin. In addition, a shorter organic gate dielectric sidewall causes a larger electric field. Therefore, sidewall electron traps exhibit parasitic transistor characteristics, and the parasitic channel experiences premature conduction, triggering an abnormal hump phenomenon. The mechanism of degradation is verified through electric field simulation; this mechanism is generated owing to the bias stress of the gate. These observations indicate that organic thin-film transistors should be designed with a suitable sidewall insulation thickness to reduce the influence of the sidewall electric field.

原文English
文章編號8880614
頁(從 - 到)1941-1944
頁數4
期刊IEEE Electron Device Letters
40
發行號12
DOIs
出版狀態Published - 2019 十二月

指紋

Thin film transistors
Electric fields
Degradation
Electron traps
Gate dielectrics
Insulation
Transistors
Lighting
Vacuum

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

引用此文

Chen, H. C., Tsao, Y. C., Chu, A. K., Huang, H. C., Lai, W. C., Chen, G. F., ... Hung, Y. H. (2019). Formation of Hump Effect Due to Top-Gate Bias Stress in Organic Thin-Film Transistors. IEEE Electron Device Letters, 40(12), 1941-1944. [8880614]. https://doi.org/10.1109/LED.2019.2949243
Chen, Hong Chih ; Tsao, Yu Ching ; Chu, An Kuo ; Huang, Hui Chun ; Lai, Wei Chih ; Chen, Guan Fu ; Huang, Shin Ping ; Chang, Ting Chang ; Chen, Po Hsun ; Chen, Jian Jie ; Kuo, Chuan Wei ; Zhou, Kuan Ju ; Hung, Yang Hao. / Formation of Hump Effect Due to Top-Gate Bias Stress in Organic Thin-Film Transistors. 於: IEEE Electron Device Letters. 2019 ; 卷 40, 編號 12. 頁 1941-1944.
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abstract = "This study investigated the reliability of top-gate p-type organic thin-film transistors in vacuum under positive bias stress-induced and positive bias illumination stress-induced instability degradation. The manufacturing process suggested that sidewall dielectric insulating layers are thin. In addition, a shorter organic gate dielectric sidewall causes a larger electric field. Therefore, sidewall electron traps exhibit parasitic transistor characteristics, and the parasitic channel experiences premature conduction, triggering an abnormal hump phenomenon. The mechanism of degradation is verified through electric field simulation; this mechanism is generated owing to the bias stress of the gate. These observations indicate that organic thin-film transistors should be designed with a suitable sidewall insulation thickness to reduce the influence of the sidewall electric field.",
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Chen, HC, Tsao, YC, Chu, AK, Huang, HC, Lai, WC, Chen, GF, Huang, SP, Chang, TC, Chen, PH, Chen, JJ, Kuo, CW, Zhou, KJ & Hung, YH 2019, 'Formation of Hump Effect Due to Top-Gate Bias Stress in Organic Thin-Film Transistors', IEEE Electron Device Letters, 卷 40, 編號 12, 8880614, 頁 1941-1944. https://doi.org/10.1109/LED.2019.2949243

Formation of Hump Effect Due to Top-Gate Bias Stress in Organic Thin-Film Transistors. / Chen, Hong Chih; Tsao, Yu Ching; Chu, An Kuo; Huang, Hui Chun; Lai, Wei Chih; Chen, Guan Fu; Huang, Shin Ping; Chang, Ting Chang; Chen, Po Hsun; Chen, Jian Jie; Kuo, Chuan Wei; Zhou, Kuan Ju; Hung, Yang Hao.

於: IEEE Electron Device Letters, 卷 40, 編號 12, 8880614, 12.2019, p. 1941-1944.

研究成果: Article

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AU - Chu, An Kuo

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AU - Lai, Wei Chih

AU - Chen, Guan Fu

AU - Huang, Shin Ping

AU - Chang, Ting Chang

AU - Chen, Po Hsun

AU - Chen, Jian Jie

AU - Kuo, Chuan Wei

AU - Zhou, Kuan Ju

AU - Hung, Yang Hao

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