Full system simulation and verification framework

Jing Wun Lin, Chen Chieh Wang, Chin Yao Chang, Chung-Ho Chen, Kuen-Jong Lee, Yuan Hua Chu, Jen Chieh Yeh, Ying Chuan Hsiao

研究成果: Conference contribution

11 引文 斯高帕斯(Scopus)

摘要

In this paper, we propose a framework to develop high-performance system accelerator hardware and the corresponding software at system-level. This framework is designed by integrating a virtual machine, an electronic system level platform, and an enhanced QEMU-SystemC. The enhancement includes a local master interface for fast memory transfer, and an interrupt handling hardware for software/hardware communication that enables full system simulation. Finally, the PAC DSP core is used as examples to demonstrate the proposed framework for full system simulation.

原文English
主出版物標題5th International Conference on Information Assurance and Security, IAS 2009
頁面165-168
頁數4
DOIs
出版狀態Published - 2009 十二月 1
事件5th International Conference on Information Assurance and Security, IAS 2009 - Xian, China
持續時間: 2009 八月 182009 九月 20

出版系列

名字5th International Conference on Information Assurance and Security, IAS 2009
1

Other

Other5th International Conference on Information Assurance and Security, IAS 2009
國家/地區China
城市Xian
期間09-08-1809-09-20

All Science Journal Classification (ASJC) codes

  • 計算機理論與數學
  • 電腦科學應用
  • 硬體和架構
  • 軟體

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