This paper applies heterogeneous simulation to achieve system and functional level co-verification throughout SoC design flow. It reduces high verification complexity resulted from covering software and hardware works and involving various tools. Stubs for data transport and a Verification Router for heterogeneous simulation management are proposed. A functional module is transformed from a highly abstract model to its target design progressively through a series of intermediate models. Those models can be validated as a portion of a complete SoC system model. The proposed heterogeneous verification is demonstrated with a jpeg encoder.