Functional verifications for SoC software/hardware co-design: From virtual platform to physical platform

Yi Li Lin, Alvin W.Y. Su

研究成果: Conference contribution

8 引文 斯高帕斯(Scopus)

摘要

This paper applies heterogeneous simulation to achieve system and functional level co-verification throughout SoC design flow. It reduces high verification complexity resulted from covering software and hardware works and involving various tools. Stubs for data transport and a Verification Router for heterogeneous simulation management are proposed. A functional module is transformed from a highly abstract model to its target design progressively through a series of intermediate models. Those models can be validated as a portion of a complete SoC system model. The proposed heterogeneous verification is demonstrated with a jpeg encoder.

原文English
主出版物標題Proceedings - IEEE International SOC Conference, SOCC 2011
頁面201-206
頁數6
DOIs
出版狀態Published - 2011 十二月 28
事件24th IEEE International System on Chip Conference, SOCC 2011 - Taipei, Taiwan
持續時間: 2011 九月 262011 九月 28

出版系列

名字International System on Chip Conference
ISSN(列印)2164-1676
ISSN(電子)2164-1706

Other

Other24th IEEE International System on Chip Conference, SOCC 2011
國家Taiwan
城市Taipei
期間11-09-2611-09-28

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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