The demand of ever improving functions of the electronic products has been pushing the development of Moor’s law featuring technologies. The microelectronic circuit technology has been moving towards the single digit nano era which is approaching the current technical limit. 3D packaging technology is being regarded as one of the most feasible technologies in this regard. The chips are being stacked in the 3D packaging so as to efficiently shrink the substrate landscape as well as shorten the circuit distance. The stacking relies on the thumb of art interconnect technologies which allow not only minimizing the substrate area but also the form factor of the products. One of the key interconnect technologies which has been improved to fit the need is the solder bumping. The conventional bumping technology of C4, is being moved to micro-bump with simplified solder compositions and shrunk solder volume. The dimension of the micro-bump may be one to three order less than the C4 bump and BGA solder ball. The fast reaction between solder and the major metallization layers during reflow, thermal compressing bonding, and afterwards functioning results in the vast proportion of intermetallic compounds (IMC) in the smaller solder volume micro joint. The fundamentals to consider about for monitoring the reliability of the microbump will be different from the C4 bump which has large volume fraction of solder alloy. This chapter will discuss the IMC formation and the microstructure of the microbump at the as-produced, thermal cycled stages of the 3D packaging.