GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node

Ya Chi Huang; Meng Hsueh Chiang; Shui Jinn Wang; Jerry G. Fossum

doi:10.1109/JEDS.2017.2689738

GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node

Ya Chi Huang, Meng Hsueh Chiang, Shui Jinn Wang, Jerry G. Fossum

研究成果: Article › 同行評審

65 引文斯高帕斯（Scopus）

摘要

Speed and power performances of Si-based stacked-nanowire gate-all-around (GAA) FETs and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected, compared, and physically explained based on 3-D numerical simulations. The respective device domains are also used to compare integration densities based on 6T-SRAM layouts. Predicted comparable performances and densities, with considerations of the complexity/cost of GAAFET processing versus that of the FinFET with pragmatic simplifications, suggest that the FinFET is the better choice for the future.

原文	English
文章編號	7890390
頁（從 - 到）	164-169
頁數	6
期刊	IEEE Journal of the Electron Devices Society
卷	5
發行號	3
DOIs	https://doi.org/10.1109/JEDS.2017.2689738
出版狀態	Published - 2017 5月

All Science Journal Classification (ASJC) codes

生物技術
電子、光磁材料
電氣與電子工程

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10.1109/JEDS.2017.2689738

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GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node

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