GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node

Ya Chi Huang, Meng Hsueh Chiang, Shui Jinn Wang, Jerry G. Fossum

研究成果: Article

13 引文 斯高帕斯(Scopus)

摘要

Speed and power performances of Si-based stacked-nanowire gate-all-around (GAA) FETs and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected, compared, and physically explained based on 3-D numerical simulations. The respective device domains are also used to compare integration densities based on 6T-SRAM layouts. Predicted comparable performances and densities, with considerations of the complexity/cost of GAAFET processing versus that of the FinFET with pragmatic simplifications, suggest that the FinFET is the better choice for the future.

原文English
文章編號7890390
頁(從 - 到)164-169
頁數6
期刊IEEE Journal of the Electron Devices Society
5
發行號3
DOIs
出版狀態Published - 2017 五月

All Science Journal Classification (ASJC) codes

  • Biotechnology
  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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