Gate driver circuit with fast-falling structure for high-resolution applications

Chin Hsien Tseng; Fu Hsing Chen; Po Cheng Lai; Chih-Lung Lin

Gate driver circuit with fast-falling structure for high-resolution applications

Chin Hsien Tseng, Fu Hsing Chen, Po Cheng Lai, Chih-Lung Lin

電機工程學系

研究成果: Conference contribution

摘要

This work proposes a new gate driver circuit which utilizes hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) for high-resolution panels. By using one TFT to separate the output node from the capacitor in the gate driver circuit, the driving TFT can remain high speed to pull down the output signal. Simulation results verify that the falling time reduces over 20% without enlarging the size of the driving TFT.

原文	English
主出版物標題	AM-FPD 2017 - 24th International Workshop on Active-Matrix Flatpanel Displays and Devices
主出版物子標題	TFT Technologies and FPD Materials, Proceedings
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	140-142
頁數	3
ISBN（電子）	9784990875336
出版狀態	Published - 2017 八月 8
事件	24th International Workshop on Active-Matrix Flatpanel Displays and Devices, AM-FPD 2017 - Kyoto, Japan 持續時間: 2017 七月 4 → 2017 七月 7

Other

Other	24th International Workshop on Active-Matrix Flatpanel Displays and Devices, AM-FPD 2017
國家	Japan
城市	Kyoto
期間	17-07-04 → 17-07-07

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Computational Theory and Mathematics

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@inproceedings{901ec8d3736242918ab42b7d66eef596,

title = "Gate driver circuit with fast-falling structure for high-resolution applications",

abstract = "This work proposes a new gate driver circuit which utilizes hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) for high-resolution panels. By using one TFT to separate the output node from the capacitor in the gate driver circuit, the driving TFT can remain high speed to pull down the output signal. Simulation results verify that the falling time reduces over 20% without enlarging the size of the driving TFT.",

author = "Tseng, {Chin Hsien} and Chen, {Fu Hsing} and Lai, {Po Cheng} and Chih-Lung Lin",

year = "2017",

month = aug,

day = "8",

language = "English",

pages = "140--142",

booktitle = "AM-FPD 2017 - 24th International Workshop on Active-Matrix Flatpanel Displays and Devices",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "24th International Workshop on Active-Matrix Flatpanel Displays and Devices, AM-FPD 2017 ; Conference date: 04-07-2017 Through 07-07-2017",

}

Tseng, CH, Chen, FH, Lai, PC & Lin, C-L 2017, Gate driver circuit with fast-falling structure for high-resolution applications. 於 AM-FPD 2017 - 24th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings., 8006102, Institute of Electrical and Electronics Engineers Inc., 頁 140-142, 24th International Workshop on Active-Matrix Flatpanel Displays and Devices, AM-FPD 2017, Kyoto, Japan, 17-07-04.

Gate driver circuit with fast-falling structure for high-resolution applications. / Tseng, Chin Hsien; Chen, Fu Hsing; Lai, Po Cheng; Lin, Chih-Lung.

AM-FPD 2017 - 24th International Workshop on Active-Matrix Flatpanel Displays and Devices: TFT Technologies and FPD Materials, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. p. 140-142 8006102.

研究成果: Conference contribution

TY - GEN

T1 - Gate driver circuit with fast-falling structure for high-resolution applications

AU - Tseng, Chin Hsien

AU - Chen, Fu Hsing

AU - Lai, Po Cheng

AU - Lin, Chih-Lung

PY - 2017/8/8

Y1 - 2017/8/8

N2 - This work proposes a new gate driver circuit which utilizes hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) for high-resolution panels. By using one TFT to separate the output node from the capacitor in the gate driver circuit, the driving TFT can remain high speed to pull down the output signal. Simulation results verify that the falling time reduces over 20% without enlarging the size of the driving TFT.

AB - This work proposes a new gate driver circuit which utilizes hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) for high-resolution panels. By using one TFT to separate the output node from the capacitor in the gate driver circuit, the driving TFT can remain high speed to pull down the output signal. Simulation results verify that the falling time reduces over 20% without enlarging the size of the driving TFT.

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UR - http://www.scopus.com/inward/citedby.url?scp=85034423845&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:85034423845

SP - 140

EP - 142

BT - AM-FPD 2017 - 24th International Workshop on Active-Matrix Flatpanel Displays and Devices

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 24th International Workshop on Active-Matrix Flatpanel Displays and Devices, AM-FPD 2017

Y2 - 4 July 2017 through 7 July 2017

ER -