Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability

C. J. Su, T. C. Hong, Y. C. Tsou, F. J. Hou, P. J. Sung, M. S. Yeh, C. C. Wan, K. H. Kao, Y. T. Tang, C. H. Chiu, C. J. Wang, S. T. Chung, T. Y. You, Y. C. Huang, C. T. Wu, K. L. Lin, G. L. Luo, K. P. Huang, Y. J. Lee, T. S. ChaoW. F. Wu, G. W. Huang, J. M. Shieh, W. K. Yeh, Y. H. Wang

研究成果: Conference contribution

11 引文 斯高帕斯(Scopus)

摘要

Ge nanowire (NW) FETs exhibiting subthreshold swing (SS) of 54 mV/dec at room temperature are demonstrated with ferroelectric HfZrOx (FE-HZO) gate stack for the first time. Ion/Ioff ratios higher than 107 and 106 for p- and n-NWFETs, respectively, have been achieved by adopting the gate-all-around (GAA) configuration. Electrical biasing effects on the HZO ferroelectric reliability have been systematically investigated in this work. It is found that the polarization behavior will degrade with electrical stress time and can be recovered. The Ge HZO FinFET CMOS inverter shows experimentally voltage gain of 24.8 V/V.

原文English
主出版物標題2017 IEEE International Electron Devices Meeting, IEDM 2017
發行者Institute of Electrical and Electronics Engineers Inc.
頁面15.4.1-15.4.4
ISBN(電子)9781538635599
DOIs
出版狀態Published - 2018 一月 23
事件63rd IEEE International Electron Devices Meeting, IEDM 2017 - San Francisco, United States
持續時間: 2017 十二月 22017 十二月 6

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
ISSN(列印)0163-1918

Other

Other63rd IEEE International Electron Devices Meeting, IEDM 2017
國家/地區United States
城市San Francisco
期間17-12-0217-12-06

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 凝聚態物理學
  • 電氣與電子工程
  • 材料化學

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