General floorplanning methodology for 3D ICs with an arbitrary bonding style

Jai-Ming Lin, Chien Yu Huang

研究成果: Conference contribution

2 引文 (Scopus)

摘要

This paper proposes a general floorplanning methodology which can be applied to 3D ICs with an arbitrary bonding style. Some researches have shown that a 3D IC with the hybrid bonding style, which includes face-to-back and face-to-face, may obtain better results than that simply using the face-to-back bonding style. We respectively present an approach to assign modules to tiers for each kind of bonding style. Further, a new utilization function, called cosine-shaped function, is proposed to estimate utilizations of bins required by the analytical-based approach. Our experimental results show the cosine-shaped function can obtain a little better result than the bell-shaped function on IBM benchmarks for 2D floorplanning. We also show that the proposed 3D floorplanning methodology consumes less TSVs and induces shorter wirelength compared to previous work in the hybrid bonding style.

原文English
主出版物標題Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1199-1202
頁數4
2018-January
ISBN(電子)9783981926316
DOIs
出版狀態Published - 2018 四月 19
事件2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 - Dresden, Germany
持續時間: 2018 三月 192018 三月 23

Other

Other2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
國家Germany
城市Dresden
期間18-03-1918-03-23

指紋

Bins
Methodology
Benchmark
Module

All Science Journal Classification (ASJC) codes

  • Safety, Risk, Reliability and Quality
  • Hardware and Architecture
  • Software
  • Information Systems and Management

引用此文

Lin, J-M., & Huang, C. Y. (2018). General floorplanning methodology for 3D ICs with an arbitrary bonding style. 於 Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 (卷 2018-January, 頁 1199-1202). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/DATE.2018.8342197
Lin, Jai-Ming ; Huang, Chien Yu. / General floorplanning methodology for 3D ICs with an arbitrary bonding style. Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. 卷 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. 頁 1199-1202
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abstract = "This paper proposes a general floorplanning methodology which can be applied to 3D ICs with an arbitrary bonding style. Some researches have shown that a 3D IC with the hybrid bonding style, which includes face-to-back and face-to-face, may obtain better results than that simply using the face-to-back bonding style. We respectively present an approach to assign modules to tiers for each kind of bonding style. Further, a new utilization function, called cosine-shaped function, is proposed to estimate utilizations of bins required by the analytical-based approach. Our experimental results show the cosine-shaped function can obtain a little better result than the bell-shaped function on IBM benchmarks for 2D floorplanning. We also show that the proposed 3D floorplanning methodology consumes less TSVs and induces shorter wirelength compared to previous work in the hybrid bonding style.",
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Lin, J-M & Huang, CY 2018, General floorplanning methodology for 3D ICs with an arbitrary bonding style. 於 Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. 卷 2018-January, Institute of Electrical and Electronics Engineers Inc., 頁 1199-1202, 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018, Dresden, Germany, 18-03-19. https://doi.org/10.23919/DATE.2018.8342197

General floorplanning methodology for 3D ICs with an arbitrary bonding style. / Lin, Jai-Ming; Huang, Chien Yu.

Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. 卷 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. p. 1199-1202.

研究成果: Conference contribution

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N2 - This paper proposes a general floorplanning methodology which can be applied to 3D ICs with an arbitrary bonding style. Some researches have shown that a 3D IC with the hybrid bonding style, which includes face-to-back and face-to-face, may obtain better results than that simply using the face-to-back bonding style. We respectively present an approach to assign modules to tiers for each kind of bonding style. Further, a new utilization function, called cosine-shaped function, is proposed to estimate utilizations of bins required by the analytical-based approach. Our experimental results show the cosine-shaped function can obtain a little better result than the bell-shaped function on IBM benchmarks for 2D floorplanning. We also show that the proposed 3D floorplanning methodology consumes less TSVs and induces shorter wirelength compared to previous work in the hybrid bonding style.

AB - This paper proposes a general floorplanning methodology which can be applied to 3D ICs with an arbitrary bonding style. Some researches have shown that a 3D IC with the hybrid bonding style, which includes face-to-back and face-to-face, may obtain better results than that simply using the face-to-back bonding style. We respectively present an approach to assign modules to tiers for each kind of bonding style. Further, a new utilization function, called cosine-shaped function, is proposed to estimate utilizations of bins required by the analytical-based approach. Our experimental results show the cosine-shaped function can obtain a little better result than the bell-shaped function on IBM benchmarks for 2D floorplanning. We also show that the proposed 3D floorplanning methodology consumes less TSVs and induces shorter wirelength compared to previous work in the hybrid bonding style.

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Lin J-M, Huang CY. General floorplanning methodology for 3D ICs with an arbitrary bonding style. 於 Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. 卷 2018-January. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1199-1202 https://doi.org/10.23919/DATE.2018.8342197