Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run

Yi Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy

研究成果: Conference contribution

摘要

A novel test pattern generation flow for both DC and AC faults is presented. All faults to be processed are transformed into stuck-at faults with some constraints in a proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model which is supported by most commercial ATPG tools. This makes it possible to generate all required patterns for both DC and AC faults in one ATPG run with no need to modify the ATPG tool. A highly compact pattern set thus can be obtained which requires smaller test data volume and shorter test application time. The fault models considered in this paper include stuck-at faults, bridging faults and transition faults. Experiments on ISCAS'89, IWLS'05 and ITC'99 benchmark circuits show that, compared to the most efficient conventional methods, on average our method can reduce test pattern counts by 14.55%, 11.26% and 13.69% and reduce test application time by 25.93%, 24.47% and 31.67%, respectively, without degrading fault coverage.

原文English
主出版物標題International Test Conference 2018, ITC 2018 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781538683828
DOIs
出版狀態Published - 2019 一月 23
事件49th IEEE International Test Conference, ITC 2018 - Phoenix, United States
持續時間: 2018 十月 292018 十一月 1

出版系列

名字Proceedings - International Test Conference
2018-October
ISSN(列印)1089-3539

Conference

Conference49th IEEE International Test Conference, ITC 2018
國家United States
城市Phoenix
期間18-10-2918-11-01

指紋

Fault
Networks (circuits)
Experiments
Count
Coverage
Model
Benchmark
Experiment

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

引用此文

Kung, Y. C., Lee, K-J., & Reddy, S. M. (2019). Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run. 於 International Test Conference 2018, ITC 2018 - Proceedings [8624678] (Proceedings - International Test Conference; 卷 2018-October). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TEST.2018.8624678
Kung, Yi Cheng ; Lee, Kuen-Jong ; Reddy, Sudhakar M. / Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run. International Test Conference 2018, ITC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. (Proceedings - International Test Conference).
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abstract = "A novel test pattern generation flow for both DC and AC faults is presented. All faults to be processed are transformed into stuck-at faults with some constraints in a proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model which is supported by most commercial ATPG tools. This makes it possible to generate all required patterns for both DC and AC faults in one ATPG run with no need to modify the ATPG tool. A highly compact pattern set thus can be obtained which requires smaller test data volume and shorter test application time. The fault models considered in this paper include stuck-at faults, bridging faults and transition faults. Experiments on ISCAS'89, IWLS'05 and ITC'99 benchmark circuits show that, compared to the most efficient conventional methods, on average our method can reduce test pattern counts by 14.55{\%}, 11.26{\%} and 13.69{\%} and reduce test application time by 25.93{\%}, 24.47{\%} and 31.67{\%}, respectively, without degrading fault coverage.",
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Kung, YC, Lee, K-J & Reddy, SM 2019, Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run. 於 International Test Conference 2018, ITC 2018 - Proceedings., 8624678, Proceedings - International Test Conference, 卷 2018-October, Institute of Electrical and Electronics Engineers Inc., 49th IEEE International Test Conference, ITC 2018, Phoenix, United States, 18-10-29. https://doi.org/10.1109/TEST.2018.8624678

Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run. / Kung, Yi Cheng; Lee, Kuen-Jong; Reddy, Sudhakar M.

International Test Conference 2018, ITC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. 8624678 (Proceedings - International Test Conference; 卷 2018-October).

研究成果: Conference contribution

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N2 - A novel test pattern generation flow for both DC and AC faults is presented. All faults to be processed are transformed into stuck-at faults with some constraints in a proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model which is supported by most commercial ATPG tools. This makes it possible to generate all required patterns for both DC and AC faults in one ATPG run with no need to modify the ATPG tool. A highly compact pattern set thus can be obtained which requires smaller test data volume and shorter test application time. The fault models considered in this paper include stuck-at faults, bridging faults and transition faults. Experiments on ISCAS'89, IWLS'05 and ITC'99 benchmark circuits show that, compared to the most efficient conventional methods, on average our method can reduce test pattern counts by 14.55%, 11.26% and 13.69% and reduce test application time by 25.93%, 24.47% and 31.67%, respectively, without degrading fault coverage.

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Kung YC, Lee K-J, Reddy SM. Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run. 於 International Test Conference 2018, ITC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2019. 8624678. (Proceedings - International Test Conference). https://doi.org/10.1109/TEST.2018.8624678