TY - JOUR
T1 - Gray-based block-matching algorithm and its VLSI architecture
AU - Shiau, Yeu Horng
AU - Chen, Pei-Yin
AU - Jou, Jer-Min
PY - 1999
Y1 - 1999
N2 - In this paper, we propose an efficient gray-based block-matching algorithm (GBMA) and its VLSI architecture. Based on the gray system theory, the GBMA can determine the better motion vectors of image blocks quickly. The experimental results show that the proposed algorithm performs better than other search algorithms, such as TSS, CS, PHODS, FSS, and SES, in terms of four different measures: 1) average MSE per pixel, 2) average PSNR, 3) average prediction errors per pixel, and 4) average search points per frame. The VLSI architecture of the algorithm has been designed and implemented, and it can yield a search rate of 680 K blocks/sec with a clock rate of 66 MHz.
AB - In this paper, we propose an efficient gray-based block-matching algorithm (GBMA) and its VLSI architecture. Based on the gray system theory, the GBMA can determine the better motion vectors of image blocks quickly. The experimental results show that the proposed algorithm performs better than other search algorithms, such as TSS, CS, PHODS, FSS, and SES, in terms of four different measures: 1) average MSE per pixel, 2) average PSNR, 3) average prediction errors per pixel, and 4) average search points per frame. The VLSI architecture of the algorithm has been designed and implemented, and it can yield a search rate of 680 K blocks/sec with a clock rate of 66 MHz.
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M3 - Article
AN - SCOPUS:0033314029
SN - 1520-6130
SP - 54
EP - 63
JO - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
JF - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ER -