Hardware Acceleration Design for Embedded Operating System Scheduling

Jian He Liao, Jer-Min Jou, Cheng Hung Hsieh, Ding Yuan Lin

研究成果: Chapter

摘要

This study examines the scheduling hardware for an embedded operating system (OS). This scheduler, which implements task sorting and choosing, is deployed when a new task enters in the system. The scheduler always limits the performance of an embedded operating system, so we consider designing the scheduler within the hardware to accelerate the performance of the OS. Therefore, hardware is used which involves an inserting and removing task in the red-black tree [9] and a checking of the red-black tree with regards to whether or not its rules are being followed. Additionally, the software communicates with the hardware by sending task data and is designed specifically to build the red/black tree into the hardware. Finally, the scheduler chooses a task from the red-black tree and tells the software to execute the program. In experiments, the performance of the embedded operating system scheduling hardware improves beyond the existing software by 13%.

原文English
主出版物標題Advances in Intelligent Systems and Applications - Volume 2
主出版物子標題Proceedings of the International Computer
編輯Chang Ruay-Shiung, Peng Sheng-Lung, Lin Chia-Chen
頁面759-767
頁數9
DOIs
出版狀態Published - 2013 六月 28

出版系列

名字Smart Innovation, Systems and Technologies
21
ISSN(列印)2190-3018
ISSN(電子)2190-3026

指紋

Scheduling
Hardware
Sorting
Software
Experiments

All Science Journal Classification (ASJC) codes

  • Decision Sciences(all)
  • Computer Science(all)

引用此文

Liao, J. H., Jou, J-M., Hsieh, C. H., & Lin, D. Y. (2013). Hardware Acceleration Design for Embedded Operating System Scheduling. 於 C. Ruay-Shiung, P. Sheng-Lung, & L. Chia-Chen (編輯), Advances in Intelligent Systems and Applications - Volume 2: Proceedings of the International Computer (頁 759-767). (Smart Innovation, Systems and Technologies; 卷 21). https://doi.org/10.1007/978-3-642-35473-1_75
Liao, Jian He ; Jou, Jer-Min ; Hsieh, Cheng Hung ; Lin, Ding Yuan. / Hardware Acceleration Design for Embedded Operating System Scheduling. Advances in Intelligent Systems and Applications - Volume 2: Proceedings of the International Computer. 編輯 / Chang Ruay-Shiung ; Peng Sheng-Lung ; Lin Chia-Chen. 2013. 頁 759-767 (Smart Innovation, Systems and Technologies).
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Liao, JH, Jou, J-M, Hsieh, CH & Lin, DY 2013, Hardware Acceleration Design for Embedded Operating System Scheduling. 於 C Ruay-Shiung, P Sheng-Lung & L Chia-Chen (編輯), Advances in Intelligent Systems and Applications - Volume 2: Proceedings of the International Computer. Smart Innovation, Systems and Technologies, 卷 21, 頁 759-767. https://doi.org/10.1007/978-3-642-35473-1_75

Hardware Acceleration Design for Embedded Operating System Scheduling. / Liao, Jian He; Jou, Jer-Min; Hsieh, Cheng Hung; Lin, Ding Yuan.

Advances in Intelligent Systems and Applications - Volume 2: Proceedings of the International Computer. 編輯 / Chang Ruay-Shiung; Peng Sheng-Lung; Lin Chia-Chen. 2013. p. 759-767 (Smart Innovation, Systems and Technologies; 卷 21).

研究成果: Chapter

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Liao JH, Jou J-M, Hsieh CH, Lin DY. Hardware Acceleration Design for Embedded Operating System Scheduling. 於 Ruay-Shiung C, Sheng-Lung P, Chia-Chen L, 編輯, Advances in Intelligent Systems and Applications - Volume 2: Proceedings of the International Computer. 2013. p. 759-767. (Smart Innovation, Systems and Technologies). https://doi.org/10.1007/978-3-642-35473-1_75