Hardware Design of an Energy-Efficient High-Throughput Median Filter

Shih Hsiang Lin, Pei Yin Chen, Chang Hsing Lin

研究成果: Article同行評審

11 引文 斯高帕斯(Scopus)

摘要

This brief presents a hardware design for an energy-efficient, high-speed, and 1-D median filter. Existing architectures focus on operating speeds, thus resulting in redundant power dissipation. This brief presents an algorithm and mathematical model for controlling the clock signals attached to the circuit by analyzing the behavior of the filter, which immobilizes the data in registers and reduces not only signal transitions but also switching activities, thereby reducing the total dynamic power consumption. Furthermore, the proposed architecture provides high-speed computation. A median result can be produced in each clock cycle, and the maximum operating frequency performance is nearly independent of the filter size. The proposed architecture uses 90-nm process technology and experimental results show that the proposed method is more energy efficient than existing designs. The power consumption is reduced by 25% on average.

原文English
文章編號8249524
頁(從 - 到)1728-1732
頁數5
期刊IEEE Transactions on Circuits and Systems II: Express Briefs
65
發行號11
DOIs
出版狀態Published - 2018 11月

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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