TY - JOUR
T1 - Hardware Design of an Energy-Efficient High-Throughput Median Filter
AU - Lin, Shih Hsiang
AU - Chen, Pei Yin
AU - Lin, Chang Hsing
N1 - Funding Information:
Manuscript received September 4, 2017; revised November 12, 2017; accepted January 1, 2018. Date of publication January 8, 2018; date of current version October 29, 2018. This work was supported in part by the Ministry of Science and Technology of Taiwan under Grant MOST 105-2221-E-006-157-MY3, and in part by NOVATEK Fellowship. This brief was recommended by Associate Editor X. Zeng. (Corresponding author: Pei-Yin Chen.) The authors are with the Digital IC Design Laboratory, Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan 70101, Taiwan (e-mail: [email protected]; [email protected]; [email protected]). Digital Object Identifier 10.1109/TCSII.2018.2790425
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2018/11
Y1 - 2018/11
N2 - This brief presents a hardware design for an energy-efficient, high-speed, and 1-D median filter. Existing architectures focus on operating speeds, thus resulting in redundant power dissipation. This brief presents an algorithm and mathematical model for controlling the clock signals attached to the circuit by analyzing the behavior of the filter, which immobilizes the data in registers and reduces not only signal transitions but also switching activities, thereby reducing the total dynamic power consumption. Furthermore, the proposed architecture provides high-speed computation. A median result can be produced in each clock cycle, and the maximum operating frequency performance is nearly independent of the filter size. The proposed architecture uses 90-nm process technology and experimental results show that the proposed method is more energy efficient than existing designs. The power consumption is reduced by 25% on average.
AB - This brief presents a hardware design for an energy-efficient, high-speed, and 1-D median filter. Existing architectures focus on operating speeds, thus resulting in redundant power dissipation. This brief presents an algorithm and mathematical model for controlling the clock signals attached to the circuit by analyzing the behavior of the filter, which immobilizes the data in registers and reduces not only signal transitions but also switching activities, thereby reducing the total dynamic power consumption. Furthermore, the proposed architecture provides high-speed computation. A median result can be produced in each clock cycle, and the maximum operating frequency performance is nearly independent of the filter size. The proposed architecture uses 90-nm process technology and experimental results show that the proposed method is more energy efficient than existing designs. The power consumption is reduced by 25% on average.
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U2 - 10.1109/TCSII.2018.2790425
DO - 10.1109/TCSII.2018.2790425
M3 - Article
AN - SCOPUS:85040619324
SN - 1549-7747
VL - 65
SP - 1728
EP - 1732
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 11
M1 - 8249524
ER -