Hardware-efficient algorithm and architecture design with memory and complexity reduction for semi-global matching

Cheng Tsung Chang, Pin Wei Chen, Wen Long Chin, Shih Hsiang Chou, Yu Hua Yang

研究成果: Article同行評審

摘要

Among the stereo matching algorithms, the semi-global matching (SGM) is an efficient and high-accuracy method. However, its huge demand for memory access and high computational complexity makes it difficult to achieve a real-time and efficient processing on hardware. Based on the spatial redundancy found in the matching cost, we propose some effective techniques to reduce the requirement of on-chip and off-chip memory, while simultaneously greatly lower the computational complexity. Experimental results present that the proposed SGM algorithm reduces the computational complexity by 71%–74% and has almost the same quality of disparity map compared with the original 8-path SGM. The proposed 3-path fully-pipelined architecture is implemented on the Xilinx VCU-106 with a throughput of 1920 × 1080/54 fps. We also synthesize and layout it with TSMC 40 nm standard library, leading to an area of 8.1 mm2 with throughput of 1920 × 1080/192 fps. The million disparity estimation per second (MDE/s) of the proposed design reaches up to 50,960, which outperforms conventional ASIC implementations.

原文English
頁(從 - 到)99-105
頁數7
期刊Integration, the VLSI Journal
92
DOIs
出版狀態Published - 2023 9月

All Science Journal Classification (ASJC) codes

  • 軟體
  • 硬體和架構
  • 電氣與電子工程

指紋

深入研究「Hardware-efficient algorithm and architecture design with memory and complexity reduction for semi-global matching」主題。共同形成了獨特的指紋。

引用此