Hardware implementation for a genetic algorithm

Pei Yin Chen, Ren Der Chen, Yu Pin Chang, Leang San Shieh, H. A. Malki

研究成果: Article同行評審

25 引文 斯高帕斯(Scopus)

摘要

A genetic algorithm (GA) can find an optimal solution in many complex problems. GAs have been widely used in many applications. A flexible-very-large-scale integration intellectual property for the GA has been proposed in this paper. This algorithm can dynamically perform various population sizes, fitness lengths, individual lengths, fitness functions, crossover operations, and mutation-rate settings to meet the real-time requirements of various GA applications. It can be seen from the simulation results that our design works very well for the three examples running at an 83-MHz clock frequency.

原文English
頁(從 - 到)699-705
頁數7
期刊IEEE Transactions on Instrumentation and Measurement
57
發行號4
DOIs
出版狀態Published - 2008 四月

All Science Journal Classification (ASJC) codes

  • 儀器
  • 電氣與電子工程

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