Hardware implementation of an image interpolation method with controllable sharpness

Pei Yin Chen, Shih Hsiang Lin, Po Chun Chen

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

The technique of image scaling plays a critical role in the digital image processing applications for the coordination between different display devices. In this paper, an improved algorithm is proposed by using a controllable sharpness coefficient to obtain better resulting images under different scaling magnifications. In addition, a power saving module including a condition judgment mechanism is applied to reduce unnecessary power consumption as the scaling ratio increases. Experimental results show that the proposed architecture is still feasible for very large-scale integration implementation and effectively enhances the quality of image scaling. By using TSMC 0.13 m cell library, the synthesis results show that the circuit can achieve 300 MHz with 12.1k gate counts and cell area is 293293 m2. The total power consumption is 6.75mW.

原文English
頁(從 - 到)51-64
頁數14
期刊Journal of Information Science and Engineering
34
發行號1
DOIs
出版狀態Published - 2018 1月

All Science Journal Classification (ASJC) codes

  • 軟體
  • 人機介面
  • 硬體和架構
  • 圖書館與資訊科學
  • 計算機理論與數學

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