The Advanced Encryption Standard (AES) is used for achieving quantum-resistant cryptography when a 256-bit key is applied. This paper presents a high-throughput, seven-stage hardware pipeline architecture for SubByte computations in the AES for information security applications. Composite field arithmetic-based calculations are employed for logic optimization. The proposed architecture includes dedicated multistage multiplication processes based on Galois field polynomials for constants, squaring, and variables; thus, the critical path of SubByte computations is shortened, and the maximum operating frequency is enhanced. The proposed architecture was synthesized using a TSMC 40-nm cell library, and the throughput of the proposed architecture (34.78 Gbps) was observed to be superior to that of an existing state-of-the-art architecture by 43.47%. Moreover, our architecture was noted to consume lower dynamic power for combinational logic circuits, indicating that the proposed architecture has greater computational logic optimization than existing designs. The proposed architecture is feasible for communication security applications in the Internet of Things systems because of its high throughput and area efficiency.
All Science Journal Classification (ASJC) codes